1. Field of the Invention
The present invention relates to a synchronizing pulse generating circuit adapted for generation of synchronizing pulses (HD pulses) for use in a deflecting system of a display monitor, especially a multi-synchronization type display monitor.
2. Description of the Background Art
It is well known that a deflecting system of a multi-synchronization type display monitor requires so-called HD pulses having a width of about half of one horizontal cycle in synchronism with a horizontal synchronizing signal and having about one horizontal cycle delay from the horizontal synchronizing signal. Various restrictions are placed on the HD pulses, which will be described below.
First, the pulse width and delay amount of the HD pulses must be variable since they are to be optimum in accordance with the cycle of the horizontal synchronizing signal.
Secondly, the HD pulses require an extremely high accuracy of synchronization with the horizontal synchronizing signal. Low synchronization accuracy results in undesired, degraded picture quality.
Further, disturbances of the horizontal synchronizing signal (noises or lack of the synchronizing signal) inevitably occur on the multi-synchronization type display monitor. In such a case, the HD pulses must not be disturbed. Disturbances of the HD pulses sometimes result in breakdown of a drive transistor of the display monitor, which will be described below.
FIG. 38 is a circuit diagram of a horizontal drive circuit for the multi-synchronization type display monitor. HD pulses are applied to the base of a drive transistor. As the frequency f.sub.H of the HD pulses lowers abruptly at time t1 as shown in FIG. 39, the collector voltage V.sub.C of the drive transistor rises abruptly from V.sub.C1 and then falls to V.sub.C2, while a power supply voltage V.sub.D falls from V.sub.D1 to V.sub.D2 gently. Thus, immediately after the time t1, the drive transistor is overloaded and, in some cases, broken down.
The HD pulses arc not allowed to change suddenly upon the sudden change of the horizontal synchronizing signal input. In particular, it is significant to prevent the HD pulses from lacking when the horizontal synchronizing signal is lacking.
FIG. 40 is a circuit diagram of a conventional synchronizing pulse generating circuit used for generation of the HD pulses. Referring to FIG. 40, a synchronizing signal such as a horizontal synchronizing signal is inputted to the synchronizing pulse generating circuit at a synchronizing input terminal 501 and is then applied to a first input of a PLL circuit 502. An output 503 from the PLL circuit 502 is fed back to its second input and is also applied to a saw-tooth wave generating circuit 504. An output 505 from the saw-tooth wave generating circuit 504 is inputted to a positive input of a voltage comparator 506. The voltage comparator 506 receives a reference voltage V1 at its negative input and makes a voltage comparison between the saw-tooth wave output 505 and the reference voltage V1. An output 507 from the voltage comparator 506 is inputted to another saw-tooth wave generating circuit 508. An output 509 from the saw-tooth wave generating circuit 509 is applied to a positive input of a voltage comparator 510. The voltage comparator 510 receives a reference voltage V2 at its negative input and makes a voltage comparison between the saw-tooth wave output 509 and the reference voltage V2. An output from the voltage comparator 510 is applied to a synchronizing pulse output terminal 511 in the form of synchronizing pulses (HD pulses).
FIG. 41 is a timing chart showing the operation of the synchronizing pulse generating circuit of FIG. 40. Description will now be given on the operation of the circuit of FIG. 40 with reference to FIG. 41.
The PLL circuit 502 oscillates at about 50% duty cycle so as to ensure phase lock at the rising of the synchronizing input 501 and at the rising of the PLL output 503. The frequency range of the phase lock of the PLL circuit 502 is determined by exteriorly attached resistor R and capacitor C. The saw-tooth wave generating circuit 504 outputs the saw-tooth wave 505 in synchronism with the PLL output 503. The voltage comparator 506 makes the voltage comparison between the saw-tooth wave 505 and the reference voltage V1 to output the voltage comparison output 507. Pulses delayed by the amount t1 from the synchronizing input 501 arc provided in the form of the voltage comparison output 507. The delay amount t1 may readily be varied by changing the reference voltage V1.
The voltage comparison output 507 is applied to the saw-tooth wave generating circuit 508 which in turn outputs the saw-tooth wave 509 synchronized with the voltage comparison output 507. The voltage comparator 510 compares the saw-tooth wave output 509 with the reference voltage V2 to output the synchronizing pulses 511. The synchronizing pulses 511 have the delay t1 from the synchronizing input 501 and a pulse width t2. The delay amount t1 may be varied by changing the reference voltage V1 as above described, and the pulse width t2 may be varied by changing the reference voltage V2.
It is assumed that a pulse lack occurs in the synchronizing input 501 at time t3 or that noises are generated in the synchronizing input 501 at time 14. The oscillating frequency of the PLL circuit 502 gradually changes to a free-running frequency determined by the exteriorly attached resistor R and capacitor C. Thus, the PLL output 503 does not undergo a sudden change, attaining the stable synchronizing pulse output 511 regardless of the pulse lack or noises in the synchronizing input 501.
The conventional synchronizing pulse generating circuit as above constructed is characterized in that the synchronizing pulse output has the variable pulse width and delay amount and is stable if the synchronizing input is disturbed.
However, it is necessary for the conventional synchronizing pulse generating circuit to have the PLL circuit 502, two saw-tooth wave generating circuits 504, 508, two voltage comparators 506, 510 as well as the resistor R and capacitor C attached to the exterior of the PLL circuit 502, resulting in the provision of a large number of parts.
Further, the voltage comparison of the saw-tooth wave creates the problem that the accuracy is liable to deteriorate. Voltage changes in the saw-tooth waves 505, 509 and reference voltages V1, V2 varies the delay amount t1 and pulse width t2 of the synchronizing pulse output 511. This means increase in jitter components of the synchronizing pulse output 511, which is undesirable particularly when used as the HD pulses.